The present invention relates to a semiconductor device, and more particularly to a method that is optimal for testing a semiconductor device, which uses complementary signal pairs, and a semiconductor device incorporating a tester circuit.
In recent years, there have been demands for further expansion of functions in semiconductor devices. Further, research has been made to develop semiconductor devices having higher integration levels, lower power consumption, and higher operation speeds. This has resulted in the popularity of a system-in-package (SiP) incorporating various devices, such as a CPU, a logic device, peripheral circuits, and a memory, in a single package.
To satisfy the demand for higher operation speeds, recent semiconductor devices include differential amplifiers used in input stages of devices to enable transmission of a small amplitude signal at a high frequency. A system such as SiP that incorporates a plurality of devices is also provided with such a differential amplifier. For example, in a memory system including a memory and a controller, the controller provides a pair of complementary clock signals to the memory. Then, a differential amplifier of the memory amplifies the complementary clock signals (synthesizes the signals) to generate a clock signal used in the memory system.
An operational test is conducted on the internal devices of such a system. As shown in FIG. 1, the operational test is conducted by providing a pair of complementary signals S and /S (symbol “/” indicates inversion) from a first device 31, which functions as a testing device, to a second device 32, which functions as a tested device. The first device 31 compares an output value D output by the second device 32 with an expected value E, which is the value expected as the output value D, to determine whether or not the second device 32 is operating normally. This determines whether or not there is a defective connection between the devices 31 and 32.